Add one adder



Aug. 13, 1963 G, T. PAUL ETAL ADD ONE ADDER Filed Feb. 24. 1960 4 Sheets-Sheet 1 A ORNEY am n s @E s mr @E Inv MDN |RS mx -a no a QQ\ NWN- Qo\ wml?. no N923 wm N Nm -m l U Le O @a k2 o E lm lwfllmol I IIIII llllll l| ill i.JT l Il Jr mm la 2 lam EMO N -w .mmnugo, n www mmc w f w la www Ow@ OW@ @E .T E NQ mm, 2 .Fem .TVNSS; i m2 1: .mi Till Q N9 m9 voll n QSmQ n 59 n m: v: n: w: I 1 l I Il L I I ri ||!|!--i !-!i| V r railiili i-- 5 5 me.; we@ www o met eml se? @wenn 2;;

Aug. 13, 1963 G. T. PAUL ETAI.

ADD ONE ADDER 4 Sheets-'Sheet 2 Filed Feb. 24, 1960 Aug. 13, 1963 G. fr. PAUL ETAL ADD ONE ADDER Filed Feb. 24, 1960 V41., Sheets-Sheet 5 Aug 13, 1963 G. T. PAUL ETAL 3,100,836l

ADD ONE ADDER Filed Feb. 24j 1960 4 Sheets-Sheet 4 United States Patent O 3,100,836 ADD ONE ADDER Gerard T. Paul and @rest J. Bedrij, Poughkeepsie, NX.,

assignors to International Business Machines Corporation, New York, N .Y., a corporation of New York Filed Feb. 24, 1960, Ser. No. 10,615 Claims. (Cl. 23S-17S) 'This invention relates to electronic computers and more particularly to an electronic mechanism for performing addition.

In the usual type of digital adder, the speed at which the addition is performed is limited by the time required for carry propagation. The digital positions of the sum are sequentially generated, starting with the lowest order position. 'Ihe sum for each digital position is generated only after the previous (lower order) digital position has been summed and it has been determined if there is a carry between the digital positions.

Ilmproved adders, such as the one shown in U.S. Patent 2,879,001, High Speed Binary Adder Having Simultaneous Carry Generation, by A. Weinberger et al., achieve higher speeds by simultaneously generating a plurality of carries. As shown therein, each carry can be generated independent from any lower order carry. Hence, all the carries could theoretically be simultaneously generated.

However, limitations which are inherent in the physical components which are used prevent the construction of circuitry whereby all the carries are simultaneously generated. `In the device shown in the above reference, a scheme is disclosed whereby the digital positions are divided into groups. First, the carries in the lowest digital order group are simultaneously generated. The carries in the second level group are next simultaneously generated dependent only upon the highest order carry in the first group and upon the operand digits in the second group. 'Ilhe `third level group operates similarly, develop-q ing its own carries based solely upon the operand digits in the third groups and upon the carry from the highest digit position of the second level group. When applied to numbers with a large number of digits the speed of such systems remains limited, since the groups operate sequentially, each group generating the sum of its digital position only `after carry generation in .the next lower order group is complete.

In the invention shown herein, the augend and addend operands are subdivided into groups, each group thereby having a subaugend and subaddend. The subaugend and subaddend of the various groups are first simultaneously operated upon to produce two signals; a carry generate signal which indicates that during an addition of the particular subaugend and subaddend, the respective group of digits would generate a carry which would propagate out of the highest order digital position of the group, and

a carry propagate signal which indicates whether or notv a carry into the respective group of digital positions would propagate vthrough the respective group of digital positions.

The subaugend and subaddend digits are further simultaneously operated upon to produce a provisional sum for each group; the provisional sums being generated under the assumption that there had been no carry into each group of digital positions.' l

A high speed carry network examines the carry generate and thecarry propagateV signals and produces carry 3,100,836 Patented Aug. 13, 1963 The novel scheme shown herein adds numbers which have a large number of digits more quickly than those schemes known to the prior art. Furthermore, the circuitry of each group can be identical, and each logical circuit need not have .a large number of inputs. In the embodiment shown herein, a high speed adder is shown wherein the logical circuits have no more than four inputs.

The object of this invention is to provide an improved adder circuit.

A further object is to provide a faster circuit for adding operands with a large number of digits.

A further object is -to provide an adder circuit wherein the logical AND circuits have a limited number of inputs.

A further object is to provide a circuit adapted to modular packaging techniques.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

In the drawings:

lFlG. 1 is a block diagram showing the general organization of a preferred embodiment of this invention.

FIG. 2 is a `schematic circuit diagram showing in detail one of the first level high speed carry propagate networks shown in FIG. 1.

FIG. 3 is a schematic circuit diagram showing in detail the second and third level high speed carry propagate networks shown in FIG. 1.

IFIG. 4 is a schematic circuit diagram showing the organization of one of the minor digit groups shown in FIG. l.

In the specific embodiment shown and described herein, the digits of the binary numbers to be summed, i.e. A1 4 and B144 are divided into a plurality of groups. Each group contains four digital positions (see FIG. l).

The addition proceeds in three major steps. First, each of the circuits 101 to 116 operates on its respective A and B inputs to produce two carry functions; to wit, a carry generate funtcion, CE, and a carry propagate function Cp. Circuits 1011 to 116 also produce provisional sums which are respectively used as inputs for add one adder circuits 131- to 146. (The provisional sums will be explained in detail later.) It is important to note that each of the circuits 101 to 116 operates independently and simultaneously.

During the second step of the operation, the high speed carry network which consists of circuits 150, 151, 152, 15'3 and 155 examines the Cg and Cp functions and the end around carry C0 and generates the group carry input signals C.

Thirdly, the add one adder circuits 131 to 146 oper ate to produce the sum digits SLM. Essentially circuits 131 to 146 add one to the respective outputs of circuits 101 to 116 if circuits 150 to 153 produce the respective C input signals.

The high speed carry network is broken into levels. In the specific embodiment shown herein (see FIG. l) circuits 150, 1151, 152 and 15?` comprise the first level of the carry network, circuit 155 comprises the second level and circuit 159' is the third level carry network. The first level carry network produces carry propagate and carry generate signals which are used as inputs to the second level carry network. `The second level carry l explained in detail. Inthe following description the tour digit groups (eg. :digits l to 4, to 8, etc.) will be referred to as minor digit groups, whereas the four groups comprising digitsvl to 1,6, 17 to 32, 33 to 48, and 49 to 64 will be referred to as major digit groups.

The major groups are numbered 161, 162, M3 and `164, respectively. It should be noted that FIG. l only shows the details :of circuitry for major groups 161 and AkBk=carry generate Ak-l-Bk=carry propagate It can be seen that a .carry generate signal indicates that a carry has been produced by the respective digital position, whereas la carry propagate signal indicates `that a carry from a previous `digital position would propagate through the respective digital position.

For the sakeV of clarity, it should be noted that since (b) A+B: (AItIBH-AB the Equation a describing a carry function can be written Hence, although the circuits lill to 116 generate the function AkZBk, in explaining the carry network herein, the

` function will be written Ak--l-Bk.

The followingvsymbolic representations will be used through the specification:

k represents la speciiic digital positionV i y represent a speciiic digital position of lower order than k Ck represents a carry out of the k digital position Cgk represents fa carry generated in the k digital position Cg(k y) represents a oar-ry generated'in and propagated out of the group of digits y to k Cp(k y) represents a condition wherein a carry introduced into the y digital position would propagatethrough the k digital position i C0 V,represents an end anoun-d carry; i.e., lcarry into the least signiiicant digital position.

'Ihe embodiment shown herein contemplates the use of the type of AND, OR and Exclu-sive OR circuits shown and described in the copending application Serial No.

622,307, Transistor Switching Circuits, tiled November 1&5, l956,`now U.S. Patent 2,964,652. As will be eX- plained in detail later, when the type of circuitry shown therein is used, Ia circuit called a convert block must be interposed betwen certain of the logical blocks. The convert blocks perform no logical operation and it is not necessary that they be considered in onder to understand the invention. Hence, the invention will first be explained without reference to the convert blocks, and the function of the convert blockslwill be explained later.

Y The symboliog'y used on the drawings is as follows: A capital letter or symbol indicates the logical operation 'i performedk (ie. LA for AND; O for OR, 1 for Exclusive OR; and C for the convert block which performs no logi- .eal operation). The l and N subscripts and the -land signs refer to the speoic type of logical block used and a discussion of theseV symbols will be deferred until later. For the purpose of understanding the principle of the invention, the subscripts, the and signs, and the convert blocks may be ignored.

As is well known in the art, the carry out of the fourth digital position may be described by the following equation:

(e) 04:(1444-34)(Aa-l-BsNz'i-BZNAl-FBCO i-(At-lB-t) (A3+B3)A2B2l (Ati-3014333 Y 'el-A434 Breaking this equation into components it can be seen that the tirst series of terms (see below) represents a carry which is propagated through the fourth digital position from the zero order digital position, whereas the second series of terms represents a carry generated out of the fourth digital position. Hence,

(h) C4=VCp1-4Coi-Cg14 Likewise, as is well known in the art the carry out of the eighth digital position can be written (i) Ce=(A3lB)(/47+Bf1)(Asl-Bs)(Ari-35)@ (Atri-Ba) (Afri-B7) (As'iBs)A5B5 i-(As-l-Bs) (A7|-B7)AsBs|(8iBa)7B7 hiAsBs Breaking this equation into components as was done before, we have Y Ca=Cp5aC4`|Cg5s If the carry C8 were made dependent on the carry C4, the carry C8 would not be generated until the carry C4 was generated. To avoid this delaythe high speed carry 1 generate network 15)l generates the canry C8 from the components of C4, to wit, Cp1 4, Cg1 4, and C0.

irCps-izcca--i-Cgs-m The circuitry as defined by Equations h,'l and n above, for the generation of the input carries C4, C8 and C12 from the carry generate Cg, carry propagate Cp and end around carry C0 signals-is shown in FIG. 2.

The carry out of the 16th digitalposition could be generated by the logical circuitry described by Equation p illustrative embodiment were limited to four inputs. This specic llimitation was imposed to illustrate the type of requirement that may be satisiied by this invention. The circuitry shown herein could easily be altered to meet different circuit requirements without departing from the invention described herein. l

However, since weA are herein limited to four inputs, a second level of carry propagation was employed; namely, circuit 155. The number of levels of carry pnopagation needed depends upon the number of inputs that the logical blocks can accommodate, and the number of digital positions in the augend and addend.

'Ihe functions Cp1 16 and Cg1 16 are first generated by circuit 150 and then combined in circuit 155 with C0 to form C16. The circuitry of circuit 151') to produce Cp1 1f, and Cg1 16 is defined by `Equations qa and qb below. The circuitry in circuit 155 to produce C16 is deiined by the equation r below.

C32 and C411 are generated in the second level high speed carry network 155 by circuitry defined by Equations sa and sb.

However, the -rst term of Equation u above would require a five input AND circuit; hence, instead of generating C64 in the second level carry network 155, another level of carry propagate network, i.e. circuit 159, is used to generate C51.

The circuit 155 has logical circuitry to generate carry propagate and carry generate signals in accordance with Equations ua and ub below:

Circuit 159 (FIG. 3) which comprises `logical circuitry connected in accordance With equation ztc below, responds to signals Cp1 6.1, Cg1 1,1fand C0 and generates C64.

The carries into the last three minor groups in each of the `other major groups 162, 163 and 164 are generated in a manner similar to that previously described for generating carries C1, C8 and C12 in major group 161. The equations describing circuits 151, 152 and 153 may be obtained by merely rewriting Equations It, l, and n, increasing the subscripts of each term by four for group 162, by eight for group 163, and by twelve for group 164.

Similar to circuit 150, circuits 151, 152 and 153 also produce carry generate and carry propagate signals. The equations `dening these functions can be obtained by appropriately increasing the subscripts in Equations q and r.

Each of the circuits 101 to 116 is identical, and likewise, each of the `add one adder circuits 131 to 146 is identical. Hence, only circuits 101 and add one adder circuit 131 will be explained in detail. Equations describing the logical circuitry of the other circuits may be obtained byV appropriately increasing the subscripts of the various equations.

Circuit 101 (FIG. 4) includes the logical circuitry described by Equationsf and g above lto generate the carry generate and ycarry propagate functions. (NOTE: as previously described, that circuit 101 produces the Cp and Cg signals by using a plurality of Exclusive OR circuits rather than OR circuits.) Circuit 101 includes logical circuitry to generate a provisional sum from the subaugend which comprises the digits A1, A2, A3 and A1 and the subaddend which comprises the digits B1, B2, B3 and B1. The provisional sum assumes that there is no carry into the lowest order digital position of the group. The logical circuitry which generates the provisional sum digits PS1 to PS4 can be described by Equations va, vb, vc and vd below:

Add one adder circuit 131 adds one to the provisional sum vwhich consists of digits PS1, PS2, PS3, PS41if the carry input signal C0 is present. The iinal sum digits are designated as S1, S2, S3 and 8.1. The logical circuits in circuit 131 may be described .by Equations wa, wb, wc and wd given below:

In understanding the above equations it should be noted that certain of the logical functions (for example, A211192) appear in more than one of the equations (see Equations vb `and vc). From the standpoint of speed (to which this patent application is primarily directed) the various signals could be generated separately; however, this would be unduly wasteful of circuit components. Hence, `as shown in FIG. 4, the functions (for example, AAI-B2) are only generated once and thereafter they are used to generate a plurality of signals.

As previously stated, the embodiment of the invention shown herein contemplates that the type of logical blocks shown inthe copending United States patent application Serial No. `622,307, tiled November 15, 1956, and entitled Transistor Switching Circuits, will be used. As shown in detail in the above referenced copending application, all Ythe functions can be performed by three different transistor circuits. These can be described as an N block, a P block, and a convert block.

The N and Pjblocks each have one or more inputs and two outputs. The N block comprises a plurality of PNP transistors and the P block comprises a plurality of NPN transistors. Por conveniencethe outputs may be designated as the top' and bottom outputs, since in the drawings one output is always shown coming from the top of the output side of the box which represents the circuit, and the other `output is always shown coming from the bottom of the output side of the box which represents the circuit.

In the following discussion, reference will be made to t-wo different voltage reference levels. The rst reference level called-the N reference is ground potential, and lines wherein the voltage varies aboutrthis reference are called N lines.V The second reference, called the P reference, is acertain negative voltage level, and lines varying about this reference are called P lines. l

Thevarious signal levels are referred to as +N, -N, +P or -P meaning Irespectively more positive or more negative than the respectivereferences. The 'N blocks always have inputs which vary about the N reference ,and P blocks always have ninputs which vary about the P reference. The output of a P block -alwaysvaries about the N level and the output of an N block always varies about the P level.

Since it is sometimes desirable to have two N or two P' blocks `connected in succession, convert blocks are used to convert from an N level to a P level and vice versa. These blocks are designated as a CN block for converting from an N level to a P level and as a CP block for converting from a P level to an N level.

The operation of the N and P blocks is best shown by the following table:

N BLOCK One or more All of the Top output Bottom o the inputs inputs output -N +P -P +N -P +P P BLOCK +P -N +N -P +N -N tive OR, operation. Furthermore, by combining two orv more blocks one can obtain the positive or negative exclusive OR functions. Y

The meaning, with reference to the blocks used, of the positivey andtnegative AND and OR functions is shown by the table'below:

' Function Y All inputs One or more v Bottom Y inputs output A -l- -l- It should be noted, however, that the invention disclosed herein is not lim-ited to the specitic'type of logical circuits shown. Those skilled in the art could implement this invention with any of the well known types of logical circuits.

It should" also be noted that the circuits 101 and 131 could be analyzed by examining each digital position separately. lf this were done, it would be, seen that both in circuit 101 and in circuit 131, carries propagate between the various digital positions within the group.

While the invention has been particularly shown and v described with reference to a preferred embodiment v thereof, it will be understood by those skilled in the art that `various changes in'lform and details maybe made therein without departing from the spirit land scope of the invention. Y

We claim: l v l. An adder wherein the digital positions of the augend, addend and sum farey similarly divided into la plurality of groups,` thereby `forming a plurality of subaugends, sub- -addendsgand true subsums, comprising in combination; digital input means in each respective group tor supplying signalscoded to represent the respective subaugended and subaddend; carry propagatetmeans in each respective group, responsive to the respective digit input means hor producing 1a carry propagate signal when the subaugend and subaddend values are such that during their addition a carry into the least significant digital positions :of the respective group would propagate through the 'entire respective .group of digital positions, carry generate means in each respective group responsive to the ydigit input means r.for producing a carry generate signal when `the respective subaugend and subaddend values are such that during their addition a carry would propagate out of the respective group of digital positions irrespective of whether there was a carry into the respective group, means in each respective group responsive to said digital input means for generating output signals representing la provisional subsum of the'subaugend and subaddend of the respective group, carry input means `associated with each group responsive to the carry generate and carry propagate means of groups or lower digital order `for producing a carry input signal for each group, and ladd yone `adder means in each group responsive to lthe respective groups summing means and to the carry input means for producing signals coded to represent the true suhsum of the respective group.V

2. An Iadder wherein the digital positions of the augend, addend and sum are successively subdivided -a plurality of times thereby forming groups within groups in a plurality of size levels, the groups ont [all but the lowest size level having a relationship of higher level in respect to groups 0f next lower level, each group yof digital positions thereby having a subaugend, a subaddend, Iand true subsum, vcornprising in combination; digital input means in each of the lowest level groups for supplying signals coded to represent the respective subaugend and subraddend, carry input means for the least signilicant digital position of each of said lowest level groups, carry propagate means in each of said lowestlevel groups, responsive to the respective digit input means for producing a carry propagate signal V when the subaugend and subaddend values `are such that during their addition a carry into the carry input means of the least signicant digital position of said lowest level group would propagate throughthe entire respective group of digital positions, carry generate means in each of said lowest level groups, responsive to the respective digit input means for producing a carry generate signal when the respective subaugend and subacldend values lare such that during their addition a carry would propagate out of the respective group of digital positions irrespective of whether there was a carry into the respective group, higher level Vgroup carry propagate means within each higher level group adapted tov be rendered `operative when each lower level group within said higher level group produces a carry propagate signal, higher level group carry generate means within each higher level group adapted to be rendered operative in response to any of `the `following conditions:

(l) a carry generate signal vfrom the lowest order,

lower level group within said higher level )group plus.

a carry propagate signa-l from each next higher order group of said lower level groups,

(2) a carry generate signal from the next to 'lowest order group of said lower level groups plus a carry propagate signal from each next higher order group of said lower level groups, Y

(3) a carry generate signal from the next to highest order group of said lower level groups plus a carry propagate signal from the highest Iorder group of said lower level groups, or

(4) a carry generate `signal from the highest order `group lof said lower level groups, l i

group-carry input means within each higher for supplying carry signals to `(l) the least signicant position of the lowest orderk group within the next higher order group of said higher level groups, (2) the group carry propagate means of the next higher order, higher level group, and y (3) the group carry generate means of the next higher order, higher level group, v-

level group 9 said group carry input means adapted to Ibe rendered operative in response to :any of the following conditions:

(l) a carry generate signal from the carry generate means within said higher level group, or

(2) a carry propagate signal fnom the carry propagate means Within said higher level group plus a carry signal from the next lower order group yof said higher level groups, summing means in each of the smal-lest groups responsive to said digital input means lfor generating signals representin-g a provisional subsum of the respective suban-gend and subaddend, said means respectively responsive to the respective subaugend input means rand to the respective subaddend input means, and add one adder means in each of the smallest groups, responsive to `tlhe summing means `and to the respective group carry input means for producing signals coded to represent the true subsums of the respective groups.

3. rIlhe invention of claim 1 in which said carry propagate means comprises a logical circuit complex which provides an output Cpx to +3 in response to subaugend input signals AX, AHI, Ax+2, and AX+3 land to subaddend input signals Bx, BH1, BH2, and BH3 in accordance with the following Boolean equation:

wherein x is the lowest order tdigita-1 position within each of said groups in claim 1.

4. The invention of claim 1 in which said carry generate means comprises Ia logical circuit complex which provides an output Cgx to +3 in response to subaugend input signals Ax, AKH, AXH, and AM3 Iand to the sub- 10 addend input sign-als BX, BKH, BH2, and BH3 in accordance with the following Boolean equation:

wmvxirsxcxn) wherein x is the lowest order ldigital position within each said `group in claim 1.

References Cited in the ile of this patent UNITED STATES PATENTS Weinberger Mar. 24, 1959 OTHER REFERENCES Proc. Institute of Elect. Engr. (England), Transistor Logic Using Current Switching, by Morgan et al., vol. 106, No. 29, pages 467-469, September 1959 (note particularly FIG. 2).

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No., shemales* August t3q 1963 Gerard T. Paul et a1.

It is hereby certified that error appears in the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Column 3 line 39, for "through" read throughout line 112 for "represent" read represents line 5599 for "betwen" read between column 9, line 25i for' l read (AX+3VBX+3) column lO, line 3 for "(AX1+VBX+1) read (AX+1VBX+1) line 21, for "(AX+1VBX+1PSXCX 1) read n Signed and sealed this 5th day of May 1964.

(SEAL) Attest:

ERNEST W., SWIDER EDWARD J. BRENNER Attesting Officer Commissioner of Patents 

2. AN ADDER WHEREIN THE DIGITAL POSITIONS OF THE AUGEND, ADDEND AND SUM ARE SUCCESSIVELY SUBDIVIDED A PLURALITY OF TIMES THEREBY FORMING GROUPS WITHIN GROUPS IN A PLURALITY OF SIZE LEVELS, THE GROUPS OF ALL BUT THE LOWEST SIZE LEVEL HAVING A RELATIONSHIP OF HIGHER LEVEL IN RESPECT TO GROUPS OF NEXT LOWER LEVEL, EACH GROUP OF DIGITAL POSITIONS THEREBY HAVING A SUBAUGEND, A SUBADDEND, AND TRUE SUBSUM, COMPRISING IN COMBINATION; DIGITAL INPUT MEANS IN EACH OF THE LOWEST LEVEL GROUPS FOR SUPPLYING SIGNALS CODED TO REPRESENT THE RESPECTIVE SUBAUGEND AND SUBADDEND, CARRY INPUT MEANS FOR THE LEAST SIGNIFICANT DIGITAL POSITION OF EACH OF SAID LOWEST LEVEL GROUPS, CARRY PROPAGATE MEANS IN EACH OF SAID LOWEST LEVEL GROUPS, RESPONSIVE TO THE RESPECTIVE DIGIT INPUT MEANS FOR PRODUCING A CARRY PROPAGATE SIGNAL WHEN THE SUBAUGEND AND SUBADDEND VALUES ARE SUCH THAT DURING THEIR ADDITION A CARRY INTO THE CARRY INPUT MEANS OF THE LEAST SIGNIFICANT DIGITAL POSITION OF SAID LOWEST LEVEL GROUP WOULD PROPAGATE THROUGH THE ENTIRE RESPECTIVE GROUP OF DIGITAL POSITIONS, CARRY GENERATE MEANS IN EACH OF SAID LOWEST LEVEL GROUPS, RESPONSIVE TO THE RESPECTIVE DIGIT INPUT MEANS FOR PRODUCING A CARRY GENERATE SIGNAL WHEN THE RESPECTIVE SUBAUGEND AND SUBADDEND VALUES ARE SUCH THAT DURING THEIR ADDITION A CARRY WOULD PROPAGATE OUT OF THE RESPECTIVE GROUP OF DIGITAL POSITIONS IRRESPECTIVE OF WHETHER THERE WAS A CARRY INTO THE RESPECTIVE GROUP, HIGHER LEVEL GROUP CARRY PROPAGATE MEANS WITHIN EACH HIGHER LEVEL GROUP ADAPTED TO BE RENDERED OPERATIVE WHEN EACH LOWER LEVEL GROUP WITHIN SAID HIGHER LEVEL GROUP PRODUCES A CARRY PROPAGATE SIGNAL, HIGHER LEVEL GROUP CARRY GENERATE MEANS WITHIN EACH HIGHER LEVEL GROUP ADAPTED TO BE RENDERED OPERATIVE IN RESPONSE TO ANY OF THE FOLLOWING CONDITIONS: (1) A CARRY GENERATE SIGNAL FROM THE LOWEST ORDER, LOWER LEVEL GROUP WITHIN SAID HIGHER LEVEL GROUP PLUS A CARRY PROPAGATE SIGNAL FROM EACH NEXT HIGHER ORDER GROUP OF SAID LOWER LEVEL GROUPS, 